This disclosure relates to a ferroelectric memory device such as FRAM and a method of fabricating the same and more specifically, to a ferroelectric memory device having a ferroelectric capacitor and a method of fabricating the same.
A ferroelectric material exhibits polarization when an external electric field is applied, and maintains the polarization even after removing the external electric field. Also, the ferroelectric material is a material that makes it possible to control a direction of spontaneous polarization according to a change of the electric field. The ferroelectric material can include, for example, PZT[Pb(Zr, Ti)O3], SBT[SrBi2Ta2O9] and the like. The characteristics of the ferroelectric material may be used for forming binary memory devices. Thus, extensive studies have been made of a ferroelectric memory device such as a ferroelectric random access memory (FRAM).
In order to form the ferroelectric memory device, materials such as PZT, SBT should have a perovskite structure. The method of forming the perovskite structure includes stacking the materials such as PZT, SBT in an amorphous state and then annealing them at an oxidizing ambient of a high temperature, e.g., 700xc2x0 C., to be crystallized. However, even if the material described method, the ferroelectric memory device still may suffer from drawbacks. For instance, if the ferroelectric memory device gets a physical shock during the subsequent process such as an etching process, or if a material such as hydrogen is diffused into the ferroelectric layer, the ferroelectric layer may suffer from deterioration of characteristics thereof.
FIG. 1 is a cross-sectional view of a cell (region) of a FRAM device for explaining deterioration of the characteristics after patterning of a ferroelectric capacitor. The FRAM device as shown in FIG. 1 has an adjacent pair of memory cells having a single plate line in common.
Referring to FIG. 1, an isolation layer 11 is formed at a semiconductor substrate 10 to define an active region. A gate electrode 15 having a spacer 13 is formed on the semiconductor substrate 10. A first interlayer insulating layer 17 is formed on the gate electrode 15. A bit line contact 19 is formed in the first interlayer insulating layer 17, and a bit line 21 is formed on the bit line contact 19. A second interlayer insulating layer 23 is formed to cover the first interlayer insulating layer 17 and the bit line 21. A contact plug 25 connected to a source of a cell transistor is formed to penetrate the first and second interlayer insulating layers 17 and 23. Thereafter, a titanium adhesion layer, a lower electrode layer, a ferroelectric layer, and an upper electrode layer are sequentially formed to cover the second interlayer insulating layer 23 and the contact plug 25. The titanium adhesion layer, the lower electrode layer, the ferroelectric layer, and the upper electrode layer are patterned to form a capacitor. At this time, the capacitor consists of an adhesion layer pattern 31, a lower electrode 33, a ferroelectric layer pattern 35, and an upper electrode 37. A space between two adjacent capacitors is filled with a third interlayer insulating layer 39. The process of forming the third interlayer insulating layer 39 includes stacking an insulating layer on the second interlayer insulating layer and performing a planarizing etch back with respect to the stacked insulating layer. Next, an aluminum layer is stacked on an entire surface of the substrate where the third interlayer insulating layer is formed. The aluminum layer is patterned to form a plate line 41. The plate line 41 overlaps with portions of the upper electrodes of the two capacitors. Next, a fourth interlayer insulating layer 43 is formed to cover the plate line 41. An interconnection line 45 is formed on the fourth interlayer insulating layer 43.
During the process of forming the plate line 41 as described above, the ferroelectric layer pattern 35 may suffer from deterioration of polarization thereof. As shown in FIG. 1, the plate line 41 has a peripheral region 47 illustrated as a dotted circle. FIG. 2 is a graph showing polarization reduction resulting from deterioration of the characteristics of the ferroelectric layer. When the ferroelectric layer is formed on a capacitor and etched, the characteristic thereof may be deteriorated. In this case, it is ideal that the polarization of the ferroelectric layer should be measured both before and after deterioration. Though, FIG. 2 shows the polarization measured with respect to the recovered ferroelectric layer, instead of the polarization measured before deterioration. This is because the polarization of the recovered ferroelectric layer is no higher than that of the ferroelectric layer that is not yet deteriorated. According to the graph of FIG. 2, the polarization is deteriorated due to an etching process.
Therefore, a recovery annealing should be performed with respect to the ferroelectric capacitor or the ferroelectric layer so as to cure etching damages. The recovery annealing is carried out with respect to an exposed top of the capacitor after the etching process. The recovery annealing is typically carried out in an oxygen ambient of a temperature of about 450xc2x0 C. However, the aluminum plate line is oxidized during the recovery annealing. In particular, aluminum oxide is formed at a contact area between the aluminum plate line and the upper electrode of the capacitor. As a result, the ferroelectric memory device may suffer another drawback. That is, a resistance between the upper electrode and the plate line may be increased.
Furthermore, in order to fabricate a highly integrated FRAM device, a width or an area of the overlapped portion of the plate line and the upper electrode has been decreased, and a contact resistance has been increased. Accordingly, if an oxide layer is formed at the contact area between the plate line and the upper electrode during the recovery annealing as mentioned above, the contact resistance may be increased even more. As a result, a cell memory device may not operate as effectively as possible.
Embodiments of the invention overcome the above-mentioned disadvantages of the conventional ferroelectric memory device such as FRAM. These embodiments provide a ferroelectric memory device and a method of fabricating the same, which may prevent deterioration of a ferroelectric characteristic of a ferroelectric layer during an etching process of a plate line. The etching process of the plate line is carried out on top of an upper electrode of a ferroelectric capacitor after formation of the capacitor.
Additionally, embodiments of the invention can prevent an increase in a contact resistance caused by an insulating oxide formed between an upper electrode and a plate line.